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stereo 2.8w audio power amplifier with dc volume control and selectable gain copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. ? operating voltage : 4.5v to 5v ? stereo switchable bridged/single-ended power amplifiers ? dc volume control interface , 0db to ?78db with precision scale ? supply current , i dd = 15ma at stereo btl ? low shutdown current , i dd = 0.7a ? bridge-tied load (btl) or single-ended-(se) modes operation ? output power at 1% thd+n , v dd =5v ? 2.3w/ch (typ) into a 3 ? load ? 2.0w/ch (typ) into a 4 ? load ? 1.2w/ch (typ) into a 8 ? load ? output power at 10% thd+n , v dd =5v ? 2.8w/ch (typ) into a 3 ? load ? 2.3w/ch (typ) into a 4 ? load ? 1.5w/ch (typ) into a 8 ? load ? single-ended mode at 1.0% thd+n ? 95mw/ch (typ) into 32 ? load ? depop circuitry integrated ? thermal shutdown protection and over current protection circuitry ? high supply voltage ripple rejection ? pc99 compliant ? 28-pin tssop-p (with enhanced thermal pad) power package available features general description applications pin description ? notebook and desktop computers ? multimedia monitors ? portable applications the apa4838 is a monolithic integrated circuit , which provides dc volume control , and a stereo bridged audio power amplifiers capable of producing 2.8w (2.3w) into 3 ? with less than 10% (1.0%) thd+n. apa4838 includes a dc volume control , stereo bridge-tied and single-ended audio power amplifiers , stereo docking outputs , and a selectable gain con- trol , that makes it optimally fittable for notebook pc , multimedia monitors , and other portable applications. the attenuator range of the volume control in apa4838 is from 0db (dc_vol=0.8v dd ) to ?78db (dc_vol=0v) with 31 steps. both of the depop circuitry and the thermal shutdown protection circuitry are integrated in apa4838 , that reduces pops and clicks noise during power up or shutdown mode op- eration , and protects the chip from being destroyed by over temperature failure. to simplify the audio system design , apa4838 combines a stereo bridge- tied loads (btl) mode for speaker drive and a stereo single-end (se) mode for headphone drive into a single chip , where both modes are easily switched by the hp sense input control pin signal. besides the low supply current design to increase the effi- ciency of the amplifiers , apa4838 also features a shutdown function which keeps the supply current only 0.7a (typ). shutdown gnd v dd gnd hp sense bypass right dock gain select mode mute dc vol right in beep in left in left dock gnd 10 1 2 3 4 5 6 7 8 9 11 12 13 14 right out + v dd right out - right gain 2 right gain 1 gnd left gain 1 left gain 2 left out - gnd v dd left out + 28 27 26 25 24 23 22 21 20 19 18 17 16 15
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 2 block diagram ordering and marking information package code r : ts s o p -p temp. range i : -40 to 85 c handling code tu : tube tr : tape & r eel apa4838 handling code temp. range package code apa4838 r : apa4838 xxxxx xxxxx - date code mode control mode mute hp sense volume control 31 steps beep detect - + - + power management click and pop suppression circuitry - + - + - + gain select left dock 20k ? 20k ? 20k ? 10k ? 10k ? - left out 20k ? 20k ? + right out - right out 0.068 f 20k ? 10k ? 20k ? 20k ? 10k ? 0.068 f 20k ? 20k ? right dock shutdown v dd gnd bypass bias left in 0.33 f right in 0.33 f 20k ? 200k ? 200k ? 20k ? beep in + left out - + dc_vol 20k ? 20k ? bias left gain1 left gain2 right gain1 right gain2 left audio input right audio input
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 3 symbol parameter rating unit v dd supply voltage -0.3 to 6 v v in input voltage range, hp sense, shutdown, mute, mode, gain select -0.3 to v dd +0.3 v t a operating ambient temperature range -40 to 85 c t j maximum junction temperature internally limited* 1 c t stg storage temperature range -65 to +150 c t s soldering temperature,10 seconds 260 c v esd electrostatic discharge -2000 to 2000* 2 v p d power dissipation internally limited w note: 1.apa4838 integrated internal thermal shutdown protection when junction temperature ramp up to 150c 2.human body model: c=100pf, r=1500 ? , 3 positives pulse plus 3 negative pulses 3.machine model: c=200pf, l=0.5 f, 3 positive pulses plus 3 negative pulses recommended operating conditions min. max. unit supply voltage, v dd 4.5 5.5 v shutdown, mute, mode, gain select 2 high level threshold voltage, v ih hp sense 4 v shutdown, mute, mode, gain select 1.0 low level threshold voltage, v il hp sense 3 v common mode input voltage, v icm v dd -1.0 v thermal characteristics symbol parameter value unit r thja thermal resistance from junction to ambient in free air tssop-p* 45 k/w * 5 in 2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. the thermal pad on the tssop_p package with solder on the printed circuit board. (over operating free-air temperature range unless otherwise noted.) absolute maximum ratings
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 4 electrical characteristics electrical characteristics for volume attenuators the following specifications apply for v dd = 5v. limits apply for t a = 25c electrical characteristics for btl mode operation the following specifications apply for v dd = 5v unless otherwise noted. limits apply for t a = 25c apa4838 symbol parameter test conditions min. typ. max. unit gain with v pin 7 =5v 0.5 c range attenuator range attenuation with v pin 7 =0v -65 -78 db v pin 5 =5v, bridged mode -70 a m mute attenuation v pin 5 =5v, single-ended mode -70 db apa4838 symbol parameter test conditions typ. unit v os output offset voltage v in =0v 5 mv thd=1%, f=1khz r l =3 ? r l =4 ? r l =8 ? 2.3 2.0 1.2 p o output power thd=10%, f=1khz r l =8 ? 1.5 w thd+n total harmonic distortion + noise a vd =2, f=1khz r l =4 ? , p o =1.5w r l =8 ? , p o =1w 0.07 0.07 % psrr power supply rejection ratio v ripple =100mv rms c b =2.2 f, r l =8 ? , f=1khz 70 db x talk channel separation c b =2.2 f, f=1khz, r l =8 ? 90 db snr signal-to-noise ratio v dd =5v, p o =1.1w, r l =8 ? ,a-wtd filter 95 db v n output noise voltage r l =8 ? ,a-wtd filter 30 v electrical characteristics for entire ic the following specifications apply for v dd = 5v unless otherwise noted. limits apply for t a = 25c apa4838 symbol parameter test conditions min. typ. max. unit v dd supply voltage 4.5 5.5 v i dd quiescent power supply current v in =0v, i o =0a 15 25 ma i sd shutdown current v pin 2 = v dd 0.7 2.0 a
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 5 apa4838 symbol parameter test conditions typ. unit v os output offset voltage v in =0v 5 mv thd=1%, f=1khz, r l =32 ? 95 p o output power thd=10%, f=1khz, r l =32 ? 110 mw a v = 1 , v out =1v rms , r l =10k ? , f=1khz 0.05 % thd+n total harmonic distortion plus noise p o =75mw, r l =32 ? , a v = 1, f=1khz 0.07 % psrr power supply rejection ratio v ripple =100mv rms , f=120hz, c b =2.2 f 52 db x talk channel separation c b =2.2 f, r l =8 ? , f=1khz 90 db snr signal-to-noise ratio p o =75mw, r l =32 ? , a-wtd filter 102 db v n output noise voltage r l =32 ? , a-wtd filter 20 v electrical characteristics (cont.) electrical characteristics for se mode operation (cont.) the following specifications apply for v dd = 5v unless otherwise noted. limits apply for t a = 25c pin description pin name no i/o description gnd 1, 8, 14, 20, 23 ground connection for circuitry. shutdown 2 i shutdown mode control signal input, place entire ic in shutdown mode when held high, idd=0.7ua gain select 3 i gain select input pin, logic high will switch the amplifier to external gain mode, and logic low will switch to internal unity gain. mode 4 i mode select input pin, fixed gain when logic l and gain adjustable mode when logic h. mute 5 i mute control input pin, active h. v dd 6, 16, 27 supply voltage input pin dc_vol 7 i volume control function input pin. right dock 9 o right docking output pin right in 10 i right channel audio input pin beep in 11 i beep signal input pin left in 12 i left channel audio input pin left dock 13 o right docking output pin left out + 15 o left channel positive output pin left out - 17 o left channel negative output pin left gain 2 18 connect pin 2 of the external gain setting resistor for left channel left gain 1 19 connect pin 1 of the external gain setting resistor for left channel hp sense 21 i headphone sense control pin
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 6 pin name no i/o description bypass 22 bypass pin right gain 1 24 connect pin 1 of the external gain setting resistor for right channel right gain 2 25 connect pin 2 of the external gain setting resistor for right channel right out - 26 o right channel negative output pin right out + 28 o right channel positive output pin mute gain select mode hp sense gain mode of power amplifier dc vol. control btl output se output 0000unity gain settingfixed levelvol. fixed - 0001unity gain settingfixed level muted vol. fixed 0010unity gain settingadjustablevol. adjustable - 0011unity gain settingadjustable mutedvol. adjustable 0100external gain settingfixed levelvol. fixed - 0101external gain settingfixed level muted vol. fixed 0110external gain settingadjustablevol. adjustable - 0111external gain settingadjustable mutedvol. adjustable 1 x x x - - muted muted truth table for logic inputs pin description (cont.)
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 7 typical application circuit mode control mute hp sense volume control 31 steps beep detect - + - + power management click and pop suppression circuitry - + - + - + internal gain select 20k ? 20k ? 20k ? 10k ? 10k ? - left out 20k ? 20k ? + right out - right out 0.068 f 20k ? 10k ? 20k ? 20k ? 10k ? 0.068 f 20k ? 20k ? v dd gnd bypass bias left dock 0.33 f right in 0.33 f 20k ? 200k ? 200k ? 20k ? beep in + left out - + 220 f pin ring headphone jack sleeve control pin tip 1k ? 100k ? to control pin on headphone jack 100k ? right audio input shutdown v dd v dd 1 f dc vol control 17 19 15 1k ? to hp sense circuit 220 f + + 18 28 26 25 24 2 22 1,8,14,20,23 2.2 f 0.1 f 0.1 f 0.1 f 6,16,27 9 10 11 12 7 3 21 v dd 5 4 mode 13 20k ? left in + + 20k ? right dock r_var bias left audio input
copyright ? anpec electronics corp. rev. a.1 - feb., 2003 apa4838 www.anpec.com.tw 8 application information gain (db) voltage range (% of vdd) voltage range (vdd=5v) low high recommended low high recommended 0 77.5% 100.00% 100.000% 3.875 5.000 5.000 -1 75.0% 78.5% 76.875% 3.750 3.938 3.844 -2 72.5% 76.25% 74.375% 3.625 3.813 3.719 -3 70.0% 73.75% 71.875% 3.500 3.688 3.594 -4 67.5% 71.25% 69.375% 3.375 3.563 3.469 -5 65.0% 68.75% 66.875% 3.250 3.438 3.344 -6 62.5% 66.25% 64.375% 3.125 3.313 3.219 -8 60.0% 63.75% 61.875% 3.000 3.188 3.094 -10 57.5% 61.25% 59.375% 2.875 3.063 2.969 -12 55.0% 58.75% 56.875% 2.750 2.938 2.844 -14 52.5% 56.25% 54.375% 2.625 2.813 2.719 -16 50.0% 53.75% 51.875% 2.500 2.688 2.594 -18 47.5% 51.25% 49.375% 2.375 2.563 2.469 -20 45.0% 48.75% 46.875% 2.250 2.438 2.344 -22 42.5% 46.25% 44.375% 2.125 2.313 2.219 -24 40.0% 43.75% 41.875% 2.000 2.188 2.094 -26 37.5% 41.25% 39.375% 1.875 2.063 1.969 -28 35.0% 38.75% 36.875% 1.750 1.938 1.844 -30 32.5% 36.25% 34.375% 1.625 1.813 1.719 -32 30.0% 33.75% 31.875% 1.500 1.688 1.594 -34 27.5% 31.25% 29.375% 1.375 1.563 1.469 -36 25.0% 28.75% 26.875% 1.250 1.438 1.344 -38 22.5% 26.25% 24.675% 1.125 1.313 1.219 -40 20.0% 23.75% 21.875% 1.000 1.188 1.094 -42 17.5% 21.25% 19.375% 0.875 1.063 0.969 -44 15.0% 18.75% 16.875% 0.750 0.937 0.844 -46 12.5% 16.25% 14.375% 0.625 0.812 0.719 -48 10.0% 13.75% 11.875% 0.500 0.687 0.594 -50 7.5% 11.25% 9.375% 0.375 0.562 0.469 -52 5.0% 8.75% 6.875% 0.250 0.437 0.344 -78 0.0% 6.25% 0.000% 0.000 0.312 0.000 volume control table
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 9 0.01 10 0.1 1 100m 3 500m 1 0.01 10 0.1 1 20 20k 100 1k 0.01 10 0.1 1 10m 3 100m 1 0.01 10 0.1 1 20 20k 100 1k typical characteristics thd+n (%) thd+n vs. output power output power (w) thd+n vs. frequency frequency (hz) thd+n (%) thd+n vs. output power output power (w) thd+n (%) thd+n vs. frequency thd+n (%) frequency (hz) av=2 vdd=5v rl=3 ? po=1.8w btl av=4 av=8 vdd=5v rl=3 ? av=2 btl f=20khz f=1khz f=20hz vdd=5v rl=4 ? av=2 btl f=20khz f=1khz f=20hz av=2 vdd=5v rl=4 ? po=1.5w btl av=4 av=8
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 10 0.01 10 0.1 1 10m 500m 100m 0.01 10 0.1 1 20 20k 100 1k 0.01 10 0.1 1 10m 2 100m 1 0.01 10 0.1 1 20 20k 100 1k thd+n (%) thd+n vs. output power output power (w) thd+n vs. frequency frequency (hz) thd+n (%) thd+n vs. output power output power (w) thd+n (%) thd+n vs. frequency thd+n (%) frequency (hz) av=2 vdd=5v rl=8 ? po=1.0w btl av=4 av=8 vdd=5v rl=8 ? av=2 btl f=20khz f=1khz f=20hz vdd=5v rl=8 ? av=1 se f=20khz f=1khz f=20hz av=1 vdd=5v rl=8 ? po=250mw se av=2 av=4 typical characteristics (cont.)
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 11 0.01 10 0.1 1 10m 200m 50m 100m 0.01 10 0.1 1 20 20k 100 1k 0.01 10 0.1 1 10m 300m 100m 0.01 10 0.1 1 20 20k 100 1k thd+n (%) thd+n vs. output power output power (w) thd+n vs. frequency frequency (hz) thd+n (%) thd+n vs. output power output power (w) thd+n (%) thd+n vs. frequency thd+n (%) frequency (hz) av=1 vdd=5v rl=16 ? po=150mw se av=2 av=4 vdd=5v rl=16 ? av=1 se f=20khz f=1khz f=20hz vdd=5v rl=32 ? av=1 se f=20khz f=1khz f=20hz av=1 vdd=5v rl=32 ? po=75mw se av=2 av=4 typical characteristics (cont.)
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 12 -120 +0 -100 -80 -60 -40 -20 20 20k 100 1k -120 +0 -100 -80 -60 -40 -20 20 20k 100 1k 0.01 10 0.1 1 100m 3 500m 2 0.01 10 0.1 1 20 20k 100 1k thd+n (%) thd+n vs. output swing output swing (v rhs ) crosstalk vs. frequency frequency (hz) crosstalk (db) crosstalk vs. frequency frequency (hz) crosstalk (db) thd+n vs. frequency thd+n (%) frequency (hz) av=1 vdd=5v rl=10k ? vo=1vrms se av=2 av=4 vdd=5v rl=10k ? av=1 se f=20khz f=1khz f=20hz vdd=5v rl=32 ? po=75mw av=2 se r-ch to l-ch vdd=5v rl=8 ? po=1.0w av=2 btl l-ch to r-ch r-ch to l-ch l-ch to r-ch typical characteristics (cont.)
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 13 1 100 10 20 20k 100 1k 1 100 10 20 20k 100 1k 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.5 1 1.5 2 2.5 0 5 10 15 20 25 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 noise floor ( v rms ) noise floor vs. frequency frequency (hz) supply current vs. supply voltage supply voltage (v) supply current (ma) power dissipation vs. output power output power (w) power dissipation (w) noise floor vs. frequency noise floor ( v rms ) frequency (hz) no filter vdd=5v rl=8 ? av=2 btl rl=3 ? btl se no load a-weight no filter vdd=5v rl=32 ? av=1 se a-weight rl=4 ? rl=8 ? vdd=5v av=2 btl typical characteristics (cont.)
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 14 0 20 40 60 80 100 120 140 160 2.5 3 3.5 4 4.5 5 5.5 0 0.5 1 1.5 2 2.25 2.5 3 3.5 4 4.5 5 5.5 -8 0 -7 6 -7 2 -6 8 -6 4 -6 0 -5 6 -5 2 -4 8 -4 4 -4 0 -3 6 -3 2 -2 8 -2 4 -2 0 -1 6 -1 2 -8 -4 0 4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 output gain (db) gain vs. voltage, 5v, se dc vol input voltage (v) output power vs. supply voltage supply voltage (v) output power (w) output power vs. supply voltage supply voltage (v) output power (mw) power dissipation vs. output power power dissipation (w) output power (w) vdd=5v av=1 se rl=8 ? av=2 btl thd+n=10% rl=8 ? rl=16 ? rl=32 ? vdd=5v av=2 se thd+n=1% rl=32 ? av=1 se thd+n=10% thd+n=1% typical characteristics (cont.)
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 15 -100 +0 -80 -60 -40 -20 20 20k 100 1k -100 +0 -80 -60 -40 -20 20 20k 100 1k 0 100 200 300 400 500 600 700 800 4 8 16 24 32 40 48 56 64 0 0.5 1 1.5 2 2.5 3 4 8 16 24 32 40 48 56 64 typical characteristics (cont.) output power (mw) output power vs. load resistance load resistance ( ? ) psrr vs. frequency frequency (hz) ripple rejection ratio (db) psrr vs. frequency frequency (hz) ripple rejection ratio (db) output power vs. load resistance output power (w) load resistance ( ? ) vdd=5v av=2 btl vdd=5v av=1 se gain adjustable vdd=5v vin=100mvrms rl=8 ? cbypass=2.2 f av=2 btl thd+n=10% thd+n=1% thd+n=10% thd+n=1% fixed gain mode gain adjustable vdd=5v vin=100mvrms rl=8 ? cbypass=2.2 f av=1 se fixed gain mode
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 16 -0 +12 +2 +4 +6 +8 +10 20 20k 100 1k typical characteristics (cont.) gain (db) frequency (hz) cf=0.068 f cf=0.22 f cf=0.1 f vdd=5v rl=8 ? av=2v/v btl gain vs. frequency
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 17 application descriptions btl operation the apa4838 output stage (power amplifier) has two pairs of operational amplifiers internally, allowed for different amplifier configurations for each channel. vbias -out +out rl op1 op2 gain 1 gain 2 volume control amplifier output signal figure 1: apa4838 power amplifier internal configu- ration (each channel) the power amplifier op1 gain is setting by internal unity-gain or external gain setting which is selected from gain select pin and the audio input signal come from internal volume control block, while the second amplifier op2 is internally fixed in a unity-gain, in- verting configuration. figure 1 shows that the output of op1 is connected to the input to op2, which re- sults in the output signals of with both amplifiers with identical in magnitude, but out of phase 180. consequently, the differential gain for each channel is 2x (gain of se mode). by driving the load differentially through outputs -out and +out, an amplifier configuration commonly re- ferred to as bridged mode is established. btl mode operation is different from the classical single-ended se amplifier configuration where one side of its load is connected to ground. btl operation (cont.) a btl amplifier design has a few distinct advantages over the se configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. four times the output power is possible as compared to a se amplifier under the same conditions. a btl configuration, such as the one used in apa4838, also creates a second advantage over se amplifiers. since the differential outputs, +right out, -right out, +left out, and -left out, are biased at half-supply, no need dc voltage exists across the load. this elimi- nates the need for an output coupling capacitor which is required in a single supply, se configuration. single-ended operation consider the single-supply se configuration shown application circuit. a coupling capacitor is required to block the dc offset voltage from reaching the load. these capacitors can be quite large (approximately 33 f to 1000 f) so they tend to be expensive, oc- cupy valuable pcb area, and have the additional drawback of limiting low-frequency performance of the system (refer to the output coupling capacitor). the rules described still hold with the addition of the following relationship: 1 cbypass x 125k ? 1 rici << 1 r l c c (1)
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 18 application descriptions (cont.) output se/btl operation the ability of the apa4838 to easily switch between btl and se modes is one of its most important costs saving features. this feature eliminates the require- ment for an additional headphone amplifier in appli- cations where internal stereo speakers are driven in btl mode but external headphone or speakers must be accommodated. internal to the apa4838, two separate amplifiers drive ?out and +out for each channel (see figure 1). the hp sense input controls the operation of the follower amplifier that drives +left out and +right out. ? when hp sense is held low, the op2 is turn on and the apa4838 is in the btl mode. ? when hp sense is held high, the op2 is in a high output impedance state, which configures the apa4838 as se driver from -out. i dd is reduced by approximately one-half in se mode. control of the hp sense input can be a logic-level ttl source or a resistor divider network or the ste- reo headphone jack with switch pin as shown in ap- plication circuit. ring headphone jack sleeve control pin tip 1k ? vdd 100k ? hp sense figure 2: hp sense input selection by phonejack plug output se/btl operation (cont.) in figure 2, input hp sense operates as follows: when the phonejack plug is inserted, the 1k ? resis- tor is disconnected and the hp sense input is pulled high and enables the se mode. when this input goes high level, the +out amplifier is shutdown causing the speaker to mute. the -out amplifier then drives through the output capacitor (c c ) into the headphone jack. when there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by re- sistors 100k ? and 1k ? . resistor 1k ? then pulls low the hp sense pin, enabling the btl function. docking output signal apa4835 internal first amplifier is used as audio sig- nal pre-amplfier and feedback resistor is connected between dock output pin and audio input pin. however, the internal first amplifier?s closed-loop gain can be adjusted using external resistors. use equa- tion 2 to determine the input and feedback resistor values for a desired gain. the dock output signal provides low distortion audio quality for light driving output. ex. active speaker, monitors or audio/visual equipment. these two out- puts can driving load of >1k ? with rail-to-rail output and output coupling capacitor is required when using these outputs. r f ri (2) a v = -
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 19 this leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. for this reason a low-leakage tantalum or ceramic ca- pacitor is the best choice. when polarized capaci- tors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at v dd /2, which is likely higher that the source dc level. please note that it is impor- tant to confirm the capacitor polarity in the application. effective bypass capacitor, cbypass input capacitor, ci (cont.) typical values for the output coupling capacitors are 0.33f to 1.0f. if polarized coupling capacitors are used, connect their ?+? terminals to the respective output pin. the right dock and left dock channel outputs sig- nal are also used to driving internal volume control amplifier. in the typical application an input capacitor, ci, is re- quired to allow the amplifier to bias the input signal to the proper dc level for optimum operation. in this case, ci and the minimum input impedance ri form a high-pass filter with the corner frequency determined in the follow equation: f c (highpass)= docking output signal (cont.) input capacitor, ci 1 2 rici (3) the value of ci is important to consider as it directly affects the low frequency performance of the circuit. consider the example where ri is 100k ? and the specification calls for a flat bass response down to 40hz. equation is reconfigured as follow: consider to input resistance variation, the ci is 0.04 f so one would likely choose a value in the range of 0.1 f to 1.0 f. a further consideration for this capacitor is the leak- age path from the input source through the input net- work (ri+rf, ci) to the load. ci= 1 2 rif c (4) as other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. the capacitors located on the bypass and power supply pins should be as close to the device as possible. the effect of a larger half supply bypass capacitor will improve psrr due to increased half- supply stability. typical application employ a 5v regu- lator with 1.0 f and a 0.1 f bypass as supply filtering. this does not eliminate the need for bypassing the supply nodes of the apa4838. the selection of by- pass capacitors, especially cbypass, is thus depen- dent upon desired psrr requirements, click and pop performance. 1 cbypass x 125k ? << 1 rici (5) application descriptions (cont.) to avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the relationship shown in equation (5) should be maintained.
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 20 effective bypass capacitor, cbypass (cont.) the bypass capacitor is fed from a 125k ? resistor inside the amplifier. bypass capacitor, cbypass, val- ues of 3.3 f to 10 f ceramic or tantalum low-esr capacitors are recommended for the best thd and noise performance. the bypass capacitance also effects to the start up time. it is determined in the following equation: application descriptions (cont.) tstart up = 5 x (cbypass x 125k ? ) (6) output coupling capacitor, cc in the typical single-supply (se) configuration, an output coupling capacitor (cc) is required to block the dc bias at the output of the amplifier thus pre- venting dc currents in the load. as with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter gov- erned by equation. for example, a 330 f capacitor with an 8 ? speaker would attenuate low frequencies below 60.6hz. the main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. large values of c c are required to pass low frequencies into the load. f c (highpass)= 1 2 r l c c (7) power supply decoupling, cs the apa4838 is a high-performance cmos audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic dis- tortion (thd) is as low as possible. power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. the optimum decoupling is achieved by using two different type capacitors that target on dif- ferent type of noise on the power supply leads. for higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (esr) ceramic capacitor, typically 0.1 f placed as close as possible to the device v dd lead works best. for filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10 f or greater placed near the audio power amplifier is recommended. optimizing depop circuitry circuitry has been included in the apa4838 to mini- mize the amount of popping noise at power-up and when coming out of shutdown mode. popping oc- curs whenever a voltage step is applied to the speaker. in order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. the value of ci will also affect turn-on pops. (refer to effective bypass capacitance) the bypass voltage rise up should be slower than input bias voltage.
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 21 optimizing depop circuitry (cont.) although the bypass pin current source cannot be modified, the size of cbypass can be changed to al- ter the device turn-on time and the amount of clicks and pops. by increasing the value of cbypass, turn- on pop can be reduced. however, the tradeoff for using a larger bypass capacitor is to increase the turn- on time for this device. there is a linear relationship between the size of cbypass and the turn-on time. in a se configuration, the output coupling capacitor, c c , is of particular concern. this capacitor discharges through the internal 10k ? resistors. depending on the size of c c , the time constant can be relatively large. to reduce transients in se mode, an external 1k ? resistor can be placed in parallel with the inter- nal 10k ? resistor. the tradeoff for using this resistor is an increase in quiescent current. in the most cases, choosing a small value of ci in the range of 0.33 f to 1 f, cbypass being equal to 4. 7 f and an external 1k ? resistor should be placed in parallel with the internal 10k ? resistor should pro- duce a virtually clickless and popless turn-on. a high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. so it is advantageous to use low-gain configurations. application descriptions (cont.) shutdown and mute function (cont.) the trigger point between a logic high and logic low level is typically 2.0v. it is best to switch between ground and the supply voltage v dd to provide maxi- mum device performance. by switching the shutdown pin to high level, the am- plifier enters a low-current state, i dd <1 a. apa4838 is in shutdown mode. on normal operating, shut- down pin pull to low level to keeping the ic out of the shutdown mode. the shutdown pin should be tied to a definite voltage to avoid unwanted state changes. the apa4838 mutes the amplifier and dock out- puts when v dd is applied to the mute pin. even while muted, the apa4838 will amplify a system alert (beep) signal whose magnitude satisfies the pcbeep de- tect circuitry. applying 0v to the mute pin returns the apa4838 to normal operation. prevent unanticipated mute behavior by connecting the mute pin to v dd or ground. do not let the mute pin float. shutdown and mute function in order to reduce power consumption while not in use, the apa4838 contains a shutdown pin to exter- nally turn off the amplifier bias circuitry. this shut- down feature turns the amplifier off when a logic high is placed on the shutdown pin. pcbeep detect circuitry apa4838 integrates a pcbeep detect circuit for note- book and computer used. when beep in signal is greater than 1/2v dd , the pcbeep mode is active. apa4838 will force to btl mode and the internal fixed gain mode. the beep in signal becomes the ampli- fier input signal and plays on the system speaker with- out coupling capacitor. use input resistor between stereo input pin and beep in to attenuate beep in signal. these resistors are shown as 200k ? devices in application circuit. use higher value resistors to reduce the gain applied to the beep signal.
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 22 pcbeep detect circuitry (cont.) if the amplifier in the mute mode, it will out of mute mode whenever pcbeep mode enable. the apa4838?s shutdown mode must be deactivated before a system alert signal is applied to beep in pin. the apa4838 will return to previous setting when it is out of pcbeep mode. the beep in pin should be tied to a ground when not used to avoid unwanted state changes. application descriptions (cont.) mode function the apa4838?s mode function has 2 states controlled by the voltage applied to the mode pin. by applying 0v to the mode pin, forces the apa4838 to fixed gain amplifier and internal volume control block will be dis- able and internal first amplifier output signal (dock) to power amplifier directly. when mode pin goes to high level, which uses the internal dc controlled vol- ume control is selected. this mode sets the amplifier?s gain according to the dc voltage applied to the dc vol control pin. do not let the mode pin float when it does not used. internal and external gain selection apa4838 provides external gain setting for base boost function or internal feedback gain setting which is decided by gain select control input. if gain se- lect pin goes high level, the gain setting will be de- fined by gain1 and gain2 pin. when gain select pin tied to low level, apa4835 power amplifier gain set- ting as unit gain by internal resistor. internal and external gain selection (cont.) in some cases a designer may want to improve the low frequency response of the bridged amplifier or incorporate a bass boost feature. refer to the figure, a resistor, r lf , and a capacitor, c lf , in parallel, can be placed in series with the feedback resistor of the bridged amplifier as seen in figure. -out op1 gain 1 gain 2 volume control amplifier output signal r i2 r f2 r lf c lf figure3: bass boost gain setting configuration fc= 1 2 r lf c lf (8) the bridged-amplifier low frequency differential gain is: fc= 2x(r f2 +r lf ) r 12 (9) using the component values shown in figure (r f2 = 20k ? ,r lf = 20k ? , and c lf = 0.068f), a first-order, - 6db pole is created at 120hz. assuming r 12 = 20k ? , the low frequency differential gain is 4. the input (c i ) and output (c o ) capacitor values must be selected for a low frequency response that covers the range of frequencies affected by the desired bass-boost operation.
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 23 table 1. efficiency vs output power in 5-v/8 ? btl systems internal and external gain selection (cont.) at low frequencies c lf is a virtual open circuit and at high frequencies, its nearly zero ohm impedance shorts r lf . the result is increased bridge-amplifier gain at low frequencies. the combination of r lf and c lf form a -6db corner frequency at application descriptions (cont.) volume adjustable and fixed gain selection the apa4838 has an internal stereo volume control whose setting is a function of the dc voltage applied to the dc vol control pin. the apa4838 volume con- trol consists of 31 steps that are individually selected by a variable dc voltage level on the dc vol control pin. the range of the steps, controlled by the dc voltage, are from 0db to -78db. each gain step cor- responds to a specific input voltage range, as shown in table. to minimize the effect of noise on the vol- ume control pin, which can affect the selected gain level, hysteresis and internal clock delay are implemented. the amount of hysteresis corresponds to half of the step width, as shown in volume control graph. for highest accuracy, the voltage shown in the ?rec- ommended voltage? column of the table is used to select a desired gain. this recommended voltage is exactly halfway between the two nearest transitions. the gain levels are 1db/step from 0db to -6db, 2db/ step from -6db to -52db, and the last step at -78db as mute mode. btl amplifier efficiency an easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. the fol- lowing equations are the basis for calculating ampli- fier efficiency. efficiency = p sup (10) p o where : efficiency of a btl configuration : p o = = rl v orms x v orms 2rl v p xv p v orms = 2 v p (11) (12) p sup = v dd x i ddrms = v dd x 2v p r l ( ) / (v dd x ) = p o p sup = v p xv p 2r l 2v p r l v p 2v dd (13) table 1 calculates efficiencies for four different out- put power levels when load is 8 ? . po (w) efficiency (%) i dd (a) v pp (v) p d (w) 0.2 26.67 0.15 2.00 0.55 0.50 41.67 0.24 2.83 0.7 1.00 58.82 0.34 4.00 0.7 1.3 68.42 0.38 4.47 0.6 **high peak voltages cause the thd to increase.
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 24 application descriptions (cont.) btl amplifier efficiency (cont.) the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. note that the internal dissipation at full output power is less than in the half power range. calculating the efficiency for a specific system is the key to proper power sup- ply design. for a stereo 1w audio system with 8 ? loads and a 5v supply, the maximum draw on the power supply is almost 3w. a final point to remember about linear amplifiers (either se or btl) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. note that in equation, v dd is in the denominator. this indicates that as v dd goes down, efficiency goes up. in other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. power dissipation whether the power amplifier is operated in btl or se modes, power dissipation is a major concern. in equation14 states the maximum power dissipation point for a se mode operating at a given supply volt- age and driving a specified load. in btl mode operation, the output voltage swing is doubled as in se mode. thus the maximum power dissipation point for a btl mode operating at the same given conditions is 4 times as in se mode. se mode : p d,max = (14) v dd 2 r l 2 2 power dissipation (cont.) btl mode : p d,max = (15) 4v dd 2 r l 2 2 since the apa4838 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. even with this substantial increase in power dissipation, the apa4838 does not require extra heatsink. the power dissipation from equation15, assuming a 5v-power supply and an 8 ? load, must not be greater than the power dissipation that results from the equation16: t j,max - t a ja p d,max = (15) for tssop-28 package with and without thermal pad, the thermal resistance ( ja ) is equal to 45 c/w and 50 c/w, respectively. since the maximum junction temperature (t j,max ) of apa4838 is 150 c and the ambient temperature (t a ) is defined by the power system design, the maximum power dissipation which the ic package is able to handle can be obtained from equation16. once the power dissipation is greater than the maximum limit (p d,max ), either the supply voltage (v dd ) must be decreased, the load impedance (r l ) must be in- creased or the ambient temperature should be reduced.
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 25 application descriptions (cont.) thermal pad considerations the thermal pad must be connected to ground. the package with thermal pad of the apa4838 requires special attention on thermal design. if the thermal design issues are not properly addressed, the apa4838 4 ? will go into thermal shutdown when driv- ing a 4 ? load. the thermal pad on the bottom of the apa4838 should be soldered down to a copper pad on the circuit board. heat can be conducted away from the thermal pad through the copper plane to ambient. if the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bot- tom plane. for good thermal conduction, the vias must be plated through and solder filled. the copper plane used to conduct heat away from the thermal pad should be as large as practical. if the ambient temperature is higher than 25c, a larger copper plane or forced-air cooling will be re- quired to keep the apa4838 junction temperature below the thermal shutdown temperature (150c). in higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the ic out of thermal shutdown.
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 26 packaging information tssop/ tssop-p ( reference jedec registration mo-153) millim eters inches dim min. max. min. max. a1.2 0.047 a1 0.00 0.15 0.000 0.006 a2 0.80 1.05 0.031 0.041 b 0.19 0.3 0.007 0.012 d 6.4 (n=20pin) 7.7 (n=24pin) 9.6 (n=28pin) 6.6 (n=20pin) 7.9 (n=24pin) 9.8 (n=28pin) 0.252 (n=20pin) 0.303 (n=24pin) 0.378 (n=28pin) 0.260 (n=20pin) 0.311 (n=24pin) 0.386 (n=28pin) d1 4.2 bsc (n=20pin) 4.7 bsc (n=24pin) 3.8 bsc (n=28pin) 0.165 bsc (n=20pin) 0.188 bsc (n=24pin) 0.150 bsc (n=28pin) e 0.65 bsc 0.026 bsc e 6.40 bsc 0.252 bsc e1 4.30 4.50 0.169 0.177 e2 3.0 bsc (n=20pin) 3.2 bsc (n=24pin) 2.8 bsc (n=28pin) 0.118 bsc (n=20pin) 0.127 bsc (n=24pin) 0.110 bsc (n=28pin) l 0.45 0.75 0.018 0.030 l1 1.0 ref 0.039ref r 0.09 0.004 r1 0.09 0.004 s0.2 0.008 8 0 8 212 ref 12 ref e2 bottom view (thermally enhanced variationds only) b d1 a1 a2 a d e 2 x e / 2 e1 e e/2 n 12 3 exposed thermal pad zone l (l1) (3) s (2) 0.25 gauge plane 1
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 27 reference jedec standard j-std-020a april 1999 reflow condition (ir/convection or vpr reflow) physical specifications pre-heat temperature 183 c peak temperature time temperature classification reflow profiles convection or ir/ convection vpr average ramp-up rate(183 c to peak) 3 c/second max. 10 c /second max. preheat temperature 125 25 c) 120 seconds max temperature maintained above 183 c 60 ? 150 seconds time within 5 c of actual peak temperature 10 ?20 seconds 60 seconds peak temperature range 220 +5/-0 c or 235 +5/-0 c 215-219 c or 235 +5/-0 c ramp-down rate 6 c /second max. 10 c /second max. time 25 c to peak temperature 6 minutes max. package reflow conditions pkg. thickness 2.5mm and all bgas pkg. thickness < 2.5mm and pkg. volume 350 mm3 pkg. thickness < 2.5mm and pkg. volume < 350mm3 convection 220 +5/-0 c convection 235 +5/-0 c vpr 215-219 c vpr 235 +5/-0 c ir/convection 220 +5/-0 c ir/convection 235 +5/-0 c terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb) lead solderability meets eia specification rsi86-91, ansi/j-std- 002 category 3.
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 28 reliability test program test item method description solderability mil-std-883d-2003 245 c , 5 sec holt mil-std-883d-1005.7 1000 hrs bias @ 125 c pct jesd-22-b, a102 168 hrs, 100 % rh , 121 c tst mil-std-883d-1011.9 -65 c ~ 150 c, 200 cycles esd mil-std-883d-3015.7 vhbm > 2kv, vmm > 200v latch-up jesd 78 10ms , i tr > 100ma carrier tape & reel dimensions t ao e w po p ko bo d1 d f p1 a j b t2 t1 c a pp lication a b c j t1 t2 w p e 330 1 100 ref 13 0.5 2 0.5 16.4 0.2 2 0.2 16 0.3 12 0.1 1.75 0.1 f d d1 po p1 ao bo ko t tssop- 28 7.5 0.1 1.5 +0.1 1.5 min 4.0 0.1 2.0 0.1 6.9 0.1 10.2 0.1 1.8 0.1 0.3 0.05 (mm)
copyright ? anpec electronics corp. rev. a. 1 - apr ., 2003 apa4838 www.anpec.com.tw 29 application carrier width cover tape width devices per reel tssop- 28 16 21.3 2000 cover tape dimensions anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 customer service

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